Phase locked loop systems (PLLs) are often integrated in very large scale integration (VLSI) devices, typically in integrated circuits (ICs) for application specific ICs (ASICs), microprocessors, and the like.
PLLs are often used as frequency synthesizers capable of generating square wave frequencies that may vary from 10 to over 200 MHz starting from an input clock signal with a frequency commonly comprised between 1 and 4 MHz.
PLLs are also used for square shaping or reshaping clock signals, for recovering digital data, etc. Whichever the type of application, PLLs must have a short-term instability of the output frequency (output jitter) as low as possible. In other words, they must be highly immune to causes of short-term instabilities, in other words, to high frequency noise.
The presence of jitter is highly detrimental in VLSI applications because the output square wave produced by the PLL system has a degree of uncertainty of the rise and fall fronts, which, if used as system clock signal, may negatively affect systems because of a reduction of the time-scale margins for a correct handling of data and of the data retention time.
Very often PLL systems must ensure a maximum instability of the switching fronts of the output signal below about 0.5 nanoseconds (ns), notwithstanding the fact that they must function in a relatively noisy "environment."
Short-term instability (jitter) in VCO, realized in an integrated circuit using VLSI CMOS technology, is primarily caused by the high frequency noise that is generated within the integrated circuit and which is injected in the VCO of a PLL through the supply rails Vdd and ground, as well as through the control voltage (Vc) line of the output frequency generated by the VCO.
A block diagram of a frequency synthesizer based on a PLL employing a voltage controlled oscillator (VCO) is depicted in FIG. 1.
Notwithstanding that the behavior of a phase locked loop is in some measure similar to that of an adaptive filter and that therefore the long-term instabilities of the input clock signal are effectively filtered, short-term instability caused by the noise coming from the supply rails and from the control voltage line remains a difficult problem to be solved, especially in VLSI devices.
Among the circuit blocks that comprise a PLL, the phase and frequency detector (PFD) and the low pass filter are intrinsically immune to short-term instabilities, while the frequency divider (1/N), generates a negligible jitter as compared with the high frequency noise that is normally present at the output of the VCO block. Therefore, it may be said that the control of jitter in a PLL requires a voltage controlled oscillator having a high immunity toward high frequency noise.
Substantially, most of the times in VLSI applications, the VCO employed for implementing a PLL consists of a voltage controlled ring oscillator. A ring oscillator offers a high gain and a great stability in a relatively simple and least burdensome way.
A typical architecture of a VCO is depicted in FIG. 2. The VCO is implemented by a plurality (odd number) of inverting (delay) stages connected in cascade, each delay stage commonly being a so-called starved-inverter comprising transistors M1, M2, M3 and M4. Each inverting stage is often followed by a Schmitt trigger circuit S1 for providing a partial filtering of short-term frequency instabilities.
In a starved-inverter, the transistors M1 and M4, controlled by the output signals produced by the voltage-current control converter, act as current sources, while the transistors M2 and M3 work essentially as digital switches by enabling the source and sink currents. Therefore, the node n1 is alternately charged and discharged, thus causing the switching of the output Schmitt trigger S1 associated with the inverting stage when its triggering thresholds (in the two switching directions) are crossed. The signals propagate through the N inverting stages of the oscillator producing a square wave output signal F-OUT.
Because of the hysteresis toward the input voltage signal switchings, the use of a Schmitt trigger at the output of each inverting stage of the ring oscillator tends to reduce the instability of the switching point of the inverting stage.
However, the noise that is injected through the control voltage line Vc as well as through the supply rails Vdd and GND, in practice, modulates the switching thresholds of the various inverting (delaying) stages that compose the ring oscillator thus causing a jitter of the switching fronts of the output signal.
Moreover, in known VCOs the output frequency varies linearly with the supply voltage and the power supply rejection (PSR) is intrinsically poor. Furthermore, the frequency produced by the VCO increases with the supply voltage and this makes the transfer function of the PLL (and therefore its stability) strongly dependent on the operating voltage unless effective but costly voltage regulation circuits are implemented. Notwithstanding the use of a Schmitt trigger at the output of each inverting delay stage of the ring oscillator, the amount of noise that is effectively filtered out is relatively modest. In a circuit working at 5V, a PSR of 10%/V is normal in known systems.
There is clearly a need for a voltage controlled oscillator (VCO) that, though being based on a ring oscillator architecture, offering a relative intrinsic stability, high gain and sturdiness with a relatively modest and least burdensome circuit complexity, has a markedly reduced sensitivity to supply voltage variations and an enhanced hysteresis of each inverting stage so as to ensure a higher rejection of high frequency noise. The circuit should remain easily integrable in CMOS technology.